1. Field of the Invention
The present invention relates to a power semiconductor device used in power conversion equipment or the like.
2. Description of the Background Art
A power semiconductor element such as a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) is used for controlling power equipment such as a motor drive inverter, an uninterruptible power supply, and a frequency conversion device. Since a rated voltage and a rated current of such power equipment tend to increase, a power semiconductor element is also required to adapt to a higher withstand voltage and a higher current.
A method of connecting a plurality of power semiconductor elements in parallel has been known as a method of increasing an amount of current that can be controlled by the power semiconductor element (see, for example, Japanese Patent Laying-Open No. 2000-92820).
In such a case as in the document above where a plurality of power semiconductor elements are connected in parallel, these elements are normally simultaneously switched by using the same drive signal. Therefore, as the number of power semiconductor elements in parallel is greater or a switching frequency is higher, switching loss (turn-on loss and turn-off loss) increases.
For example, a method described in Japanese Patent Laying-Open No. 05-291913 has been known as a method for reducing turn-off loss in power semiconductor elements connected in parallel. According to the method in this document, a first IGBT having a low saturation voltage and a long fall time and a second IGBT having a high saturation voltage and a short fall time are connected in parallel and an input resistor is inserted in a gate of the second IGBT. As the first and second IGBTs are operated by a common drive signal, a time point of disconnection of the second IGBT is later than a time point of disconnection of the first IGBT and hence a turn-off operation can be performed based on a short fall time of the second IGBT.
A similar technique is described in Japanese Patent Laying-Open No. 06-209565 and Japanese Patent Laying-Open No. 06-209566, although they do not aim to reduce switching loss. Both of the documents disclose switching circuits connected in series, each of which is constituted of a main semiconductor element and a detection semiconductor element connected in parallel thereto. Specifically, according to the technique described in former Japanese Patent Laying-Open No. 06-209565, a gate of the main semiconductor element and a gate drive circuit are connected to each other with an OFF delay circuit being interposed, and a gate of the detection semiconductor element and the gate drive circuit are connected to each other with an ON delay circuit being interposed. According to the technique described in latter Japanese Patent Laying-Open No. 06-209566, a gate of the detection semiconductor element and a gate drive circuit are connected to each other with an OFF delay circuit being interposed, and a gate of the main semiconductor element and the gate drive circuit are connected to each other with an ON delay circuit being interposed.
Japanese Patent Laying-Open No. 05-291913 above considers reduction of switching loss, however, it pays attention only to reduction of turn-off loss and it does not consider turn-on loss. In addition, since the method described in this document includes connecting the first IGBT having a low saturation voltage and a long fall time and the second IGBT having a high saturation voltage and a short fall time in parallel to each other, it is not applicable to a case where power semiconductor elements having the same characteristics are connected in parallel.